The present invention relates to the process of trimming photoresist material on semiconductor wafers and, more particularly, to trimming a photoresist material while reducing the variation of the critical dimension between photoresist lines and maximizing photoresist budget.
FIG. 1 is a cross-sectional view illustrating several conventional layers of a semiconductor wafer 10. Semiconductor wafer 10 includes a semiconductor substrate 12 formed of, e.g., silicon, that supports intermediate layers 15. Intermediate layers 15 may, for example, include a first layer 14 formed of either a conductive material (e.g. polysilicon) or a dielectric material (e.g. SiO2) depending on the type of device that is being fabricated. Intermediate layers 15 also may include a second layer 16, such as a hard mask layer or an anti-reflective coating (ARC) layer. For ease of illustration, intermediate layers 15 is shown comprising only two layers, but as is well known in the art, more layers may be provided.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. Conventionally, a layer of photoresist material 18 is deposited onto semiconductor wafer 10 over intermediate layers 15, and then patterned by a suitable process such as photolithography. In general, the wafer is exposed to light filtered by a reticle, which is a glass plate that is patterned with the desired integrated circuit layer features.
After passing through the reticle, the light impinges upon the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can be used to remove either the exposed regions (in the case of positive photoresist materials) or the unexposed regions (in the case of negative photoresist materials) of the photoresist material. In the case of positive photoresist materials, the light changes the structure and chemical properties of the photoresist material creating a number of polymerized photoresist sections. These polymerized photoresist sections are then removed using a solvent in a development process leaving a number of photoresist lines. Thereafter, the wafer is etched to remove the material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer.
FIG. 2A is a more detailed view of photoresist layer 18 after it has been patterned into a photoresist mask. In the process described above, the photoresist sections that were polymerized are removed, leaving photoresist lines 18a-d, which protect underlying layers from etching.
One important characteristic of photoresist lines is known as an aspect ratio, which compares the vertical space between lines with the horizontal space. For example, the space between photoresist lines 18a and 18b would have an aspect ratio of approximately 1:2, while the space between photoresist lines 18b and 18c would have an aspect ratio of about 5:2.
Each photoresist line 18a-d has a line width or critical dimension CD1, which determines the width of lines that will be etched in intermediate layers 15. Each photoresist line 18a-d also has a height, which is also known as a resist budget RB1. During the process of etching intermediate layers 15, photoresist lines 18a-d are also etched. Therefore, resist budget RB1 represents the amount of resist that may be consumed by the etching process. For ease of illustration, only four photoresist lines 18a-d are shown, however, as is well known in the art, numerous photoresist lines 18a-d may be formed to produce the desired feature geometries. The feature geometries will in turn enable production of the electrical interconnections intended by the manufacturer, and enable the production of a functioning integrated circuit.
One technique that engineers use to increase the operating speeds of semiconductor devices is by reducing the sizes of conductive lines within the device. Although much improvement has occurred in photolithography systems to enable the fabrication of small features sizes, current lithographic tools are still unable to define feature sizes much below about 0.18 microns. Unfortunately, the costs of developing a photolithography system to define feature sizes below 0.18 microns would be involve the manufacturing of a new tool, and therefore be prohibitively expensive. Therefore, plasma etching has been considered as a method of further reducing the critical dimension CD1, which defines feature sizes, of photoresist lines 18a-d. This technique is called photoresist trimming.
FIG. 2B illustrates patterned photoresist layer 18 during the process of photoresist trimming. After photolithography has been performed, producing photoresist lines 18a-d of, for example, about 0.18 microns, a plasma etch is performed to further reduce the critical dimensions. Photoresist lines 18a-d are bombarded with an etchant flow 20/20xe2x80x2, such as oxygen ions, using a low RF bias power to create a plasma. Etchant flow 20xe2x80x2 is distinguished from etchant flow 20 to show ions traveling toward the photoresist lines 18a-d at somewhat variable angles.
As shown in FIG. 2B, the degree of exposure that each photoresist line 18a-d has with the ion bombardment varies depending on its proximity to that of other photoresist lines. If a photoresist line is located in an open area, the sidewalls of the photoresist line are in general, fully exposed to angled etchant flow 20xe2x80x2. However, if a photoresist line is located in a dense area, the amount of etchant flow 20xe2x80x2 that reaches the lower portions of photoresist sidewalls may be greatly reduced because a large amount of etchant flow 20xe2x80x2 is blocked by the neighboring photoresist line.
For example, photoresist line 18a is isolated from other photoresist lines 18b-d. Therefore, photoresist lines 18b-d do not affect the exposure of photoresist line 18a to etchant flow 20xe2x80x2. However, because photoresist line 18c is located in close proximity to photoresist lines 18b and 18d, photoresist lines 18b and 18d block much of etchant flow 20xe2x80x2. For an etchant ion to reach the bottom of the a sidewall of photoresist line 18c, it must either travel towards the sidewall at the perfect angle, or bounce from sidewall to sidewall as shown in FIG. 2B. The amount of etchant flow 20xe2x80x2 that reaches the sidewalls of photoresist lines 18b and 18d are likewise reduced by the close proximity of photoresist line 18c. 
FIG. 2C illustrates a prior art process of photoresist trimming that has been completed. Because photoresist lines 18b-d are located in a dense area of photoresist lines, the top portions of photoresist lines 18b-d have been consumed much more rapidly by etchant flow 20/20xe2x80x2 than the bottom portions. Therefore, the sidewalls of photoresist lines 18b-d show an undesirable tapering effect, as opposed to critical dimension CD2, which is more uniform for photoresist line 18a. An ideal etch operation would leave vertical sidewalls in the surface of semiconductor wafer 10.
Because the top of densely packed photoresist lines 18b-d had a higher horizontal etch or trim rate than the bottom, critical dimension CD3 of photoresist lines 18b-d at the top is less than critical dimension CD4 of photoresist lines 18b-d at the bottom. This variation in critical dimensions CD3 and CD4 may result in errors during etching of the intermediate layers 15 below photoresist layer 18. Such errors may in turn cause inconsistencies in the conductive lines formed during fabrication, therefore adversely effecting the speed and response time of the semiconductor device.
Another problem associated with the technique of photoresist trimming is that etchant flow 20/20xe2x80x2 significantly reduces resist budget RB1 of photoresist lines 18a-d shown in FIG. 2A to resist budget RB2 in FIG. 2C. During the etching of intermediate layers 15, photoresist lines 18a-d protect the portions of intermediate layers 15 below, however during the process, the photoresist material itself will be etched away. Therefore, it is important to have an adequate resist depth or budget to ensure that there is enough photoresist material to prevent damage to the layers below. Because photoresist trimming reduces the resist budget of photoresist lines 18a-d, the process increases the chances that the layers below the photoresist material will be damaged due to insufficient resist budget.
Despite the development of photoresist trimming and the growing need for semiconductor devices with very small and conductive lines, a reliable method for preventing the tapering of photoresist lines and preserving photoresist budget is not available. In view of the foregoing, what is needed is a reliable method for trimming photoresist material from photoresist lines in semiconductor wafers while maintaining a consistent critical dimension and maximizing the resist budget of each line.
The present invention fills this need by providing a method for removing photoresist material from photoresist lines in semiconductor wafers while maintaining a consistent critical dimension and maximizing the resist budget of each line. Several inventive embodiments of the present invention are described below.
In one embodiment of the present invention, a method of removing photoresist material from a semiconductor substrate is provided. In this method, a semiconductor substrate having a patterned photoresist mask is provided. A layer comprised of polymer material is formed over the patterned photoresist mask. The layer comprised of polymer material and a portion of the patterned photoresist mask are then removed. The layer comprised of polymer material is preferably formed by introducing a process gas into a plasma environment.
In another embodiment of the present invention, a method of forming a semiconductor device is provided. In this method, a semiconductor substrate is provided. At least one intermediate layer is formed over the semiconductor substrate, after which a layer comprised of photoresist material is formed over the intermediate layers. The layer comprised of photoresist material is then patterned to form a patterned photoresist mask. A conformal layer of varying thickness comprised of polymer material is formed over then patterned photoresist mask. The layer comprised of polymer material and portions of the patterned photoresist mask are then removed. The layer comprised of polymer material is preferably formed with less thickness in a low aspect ratio area relative to a high aspect ratio area.
In yet another embodiment of the present invention, a method of removing photoresist material from a semiconductor substrate is provided. In this method, a semiconductor substrate having a patterned photoresist mask disposed thereover is provided. A conformal layer of varying thickness comprised of polymer material is formed over the patterned photoresist mask. The layer comprised of polymer material and portions of the patterned photoresist mask are then subjected to plasma etching. The layer comprised of polymer material preferably aids in preserving a resist budget of the patterned photoresist mask during removing the layer comprised of polymer material and portions of the patterned photoresist mask.
The present invention advantageously enables semiconductor devices with interconnections of less than about 0.18 microns wide to be fabricated without damaging such interconnections during the fabrication process. This is important because, as speeds at which the semiconductor devices operate increase, and feature sizes within the semiconductor device decrease, fabrication becomes an even more delicate process. The present invention reduces errors during fabrication, which could lead to a reduction in speed, or even failure of the device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the invention and studying the accompanying drawings.